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Huseyin Kayahan

Dynamic power reduction in digital pixel design for large format focal plane arrays
Digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs)
US9324745B2
Cryogenic measurements of a digital pixel readout integrated circuit for LWIR
Digital pixel readout integrated circuit architectures for LWIR
Low-power LVDS for digital readout circuits
Implementation of pixel level digital TDI for scanning type LWIR FPAs
WO/2014/082660
A new digital readout integrated circuit (DROIC) with pixel parallel A/D conversion with reduced quantization noise
Implementation of high-dynamic range pixel architecture for SWIR applications
A new digital readout integrated circuit (DROIC) with pixel parallel A/D conversion and reduced quantization noise
A fully digital readout employing extended counting method to achieve very low quantization noise
A new unit cell design with automatic input stage selection capability for increased SNR
Design of 90×8 ROIC with pixel level digital TDI implementation for scanning type LWIR FPAs
Wide Range, Process and Temperature Compensated Voltage Controlled Current Source
Design and realization of 144 x 7 TDI ROIC with hybrid integrated test structure
Design of ROIC based on switched capacitor TDI for MCT LWIR focal plane arrays
Design of a ROIC for scanning type HgCdTe LWIR focal plane arrays